chore: migrate to gitea
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236
vendor/golang.org/x/sys/cpu/cpu_x86.go
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236
vendor/golang.org/x/sys/cpu/cpu_x86.go
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// Copyright 2018 The Go Authors. All rights reserved.
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// Use of this source code is governed by a BSD-style
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// license that can be found in the LICENSE file.
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//go:build 386 || amd64 || amd64p32
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package cpu
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import "runtime"
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const cacheLineSize = 64
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func initOptions() {
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options = []option{
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{Name: "adx", Feature: &X86.HasADX},
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{Name: "aes", Feature: &X86.HasAES},
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{Name: "avx", Feature: &X86.HasAVX},
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{Name: "avx2", Feature: &X86.HasAVX2},
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{Name: "avx512", Feature: &X86.HasAVX512},
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{Name: "avx512f", Feature: &X86.HasAVX512F},
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{Name: "avx512cd", Feature: &X86.HasAVX512CD},
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{Name: "avx512er", Feature: &X86.HasAVX512ER},
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{Name: "avx512pf", Feature: &X86.HasAVX512PF},
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{Name: "avx512vl", Feature: &X86.HasAVX512VL},
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{Name: "avx512bw", Feature: &X86.HasAVX512BW},
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{Name: "avx512dq", Feature: &X86.HasAVX512DQ},
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{Name: "avx512ifma", Feature: &X86.HasAVX512IFMA},
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{Name: "avx512vbmi", Feature: &X86.HasAVX512VBMI},
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{Name: "avx512vnniw", Feature: &X86.HasAVX5124VNNIW},
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{Name: "avx5124fmaps", Feature: &X86.HasAVX5124FMAPS},
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{Name: "avx512vpopcntdq", Feature: &X86.HasAVX512VPOPCNTDQ},
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{Name: "avx512vpclmulqdq", Feature: &X86.HasAVX512VPCLMULQDQ},
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{Name: "avx512vnni", Feature: &X86.HasAVX512VNNI},
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{Name: "avx512gfni", Feature: &X86.HasAVX512GFNI},
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{Name: "avx512vaes", Feature: &X86.HasAVX512VAES},
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{Name: "avx512vbmi2", Feature: &X86.HasAVX512VBMI2},
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{Name: "avx512bitalg", Feature: &X86.HasAVX512BITALG},
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{Name: "avx512bf16", Feature: &X86.HasAVX512BF16},
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{Name: "amxtile", Feature: &X86.HasAMXTile},
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{Name: "amxint8", Feature: &X86.HasAMXInt8},
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{Name: "amxbf16", Feature: &X86.HasAMXBF16},
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{Name: "bmi1", Feature: &X86.HasBMI1},
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{Name: "bmi2", Feature: &X86.HasBMI2},
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{Name: "cx16", Feature: &X86.HasCX16},
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{Name: "erms", Feature: &X86.HasERMS},
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{Name: "fma", Feature: &X86.HasFMA},
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{Name: "osxsave", Feature: &X86.HasOSXSAVE},
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{Name: "pclmulqdq", Feature: &X86.HasPCLMULQDQ},
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{Name: "popcnt", Feature: &X86.HasPOPCNT},
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{Name: "rdrand", Feature: &X86.HasRDRAND},
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{Name: "rdseed", Feature: &X86.HasRDSEED},
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{Name: "sse3", Feature: &X86.HasSSE3},
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{Name: "sse41", Feature: &X86.HasSSE41},
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{Name: "sse42", Feature: &X86.HasSSE42},
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{Name: "ssse3", Feature: &X86.HasSSSE3},
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{Name: "avxifma", Feature: &X86.HasAVXIFMA},
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{Name: "avxvnni", Feature: &X86.HasAVXVNNI},
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{Name: "avxvnniint8", Feature: &X86.HasAVXVNNIInt8},
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// These capabilities should always be enabled on amd64:
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{Name: "sse2", Feature: &X86.HasSSE2, Required: runtime.GOARCH == "amd64"},
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}
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}
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func archInit() {
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// From internal/cpu
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const (
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// eax bits
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cpuid_AVXVNNI = 1 << 4
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// ecx bits
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cpuid_SSE3 = 1 << 0
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cpuid_PCLMULQDQ = 1 << 1
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cpuid_AVX512VBMI = 1 << 1
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cpuid_AVX512VBMI2 = 1 << 6
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cpuid_SSSE3 = 1 << 9
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cpuid_AVX512GFNI = 1 << 8
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cpuid_AVX512VAES = 1 << 9
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cpuid_AVX512VNNI = 1 << 11
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cpuid_AVX512BITALG = 1 << 12
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cpuid_FMA = 1 << 12
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cpuid_AVX512VPOPCNTDQ = 1 << 14
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cpuid_SSE41 = 1 << 19
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cpuid_SSE42 = 1 << 20
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cpuid_POPCNT = 1 << 23
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cpuid_AES = 1 << 25
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cpuid_OSXSAVE = 1 << 27
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cpuid_AVX = 1 << 28
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// "Extended Feature Flag" bits returned in EBX for CPUID EAX=0x7 ECX=0x0
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cpuid_BMI1 = 1 << 3
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cpuid_AVX2 = 1 << 5
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cpuid_BMI2 = 1 << 8
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cpuid_ERMS = 1 << 9
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cpuid_AVX512F = 1 << 16
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cpuid_AVX512DQ = 1 << 17
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cpuid_ADX = 1 << 19
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cpuid_AVX512CD = 1 << 28
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cpuid_SHA = 1 << 29
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cpuid_AVX512BW = 1 << 30
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cpuid_AVX512VL = 1 << 31
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// "Extended Feature Flag" bits returned in ECX for CPUID EAX=0x7 ECX=0x0
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cpuid_AVX512_VBMI = 1 << 1
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cpuid_AVX512_VBMI2 = 1 << 6
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cpuid_GFNI = 1 << 8
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cpuid_AVX512VPCLMULQDQ = 1 << 10
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cpuid_AVX512_BITALG = 1 << 12
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// edx bits
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cpuid_FSRM = 1 << 4
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// edx bits for CPUID 0x80000001
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cpuid_RDTSCP = 1 << 27
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)
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// Additional constants not in internal/cpu
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const (
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// eax=1: edx
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cpuid_SSE2 = 1 << 26
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// eax=1: ecx
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cpuid_CX16 = 1 << 13
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cpuid_RDRAND = 1 << 30
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// eax=7,ecx=0: ebx
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cpuid_RDSEED = 1 << 18
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cpuid_AVX512IFMA = 1 << 21
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cpuid_AVX512PF = 1 << 26
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cpuid_AVX512ER = 1 << 27
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// eax=7,ecx=0: edx
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cpuid_AVX5124VNNIW = 1 << 2
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cpuid_AVX5124FMAPS = 1 << 3
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cpuid_AMXBF16 = 1 << 22
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cpuid_AMXTile = 1 << 24
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cpuid_AMXInt8 = 1 << 25
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// eax=7,ecx=1: eax
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cpuid_AVX512BF16 = 1 << 5
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cpuid_AVXIFMA = 1 << 23
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// eax=7,ecx=1: edx
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cpuid_AVXVNNIInt8 = 1 << 4
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)
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Initialized = true
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maxID, _, _, _ := cpuid(0, 0)
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if maxID < 1 {
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return
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}
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_, _, ecx1, edx1 := cpuid(1, 0)
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X86.HasSSE2 = isSet(edx1, cpuid_SSE2)
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X86.HasSSE3 = isSet(ecx1, cpuid_SSE3)
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X86.HasPCLMULQDQ = isSet(ecx1, cpuid_PCLMULQDQ)
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X86.HasSSSE3 = isSet(ecx1, cpuid_SSSE3)
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X86.HasFMA = isSet(ecx1, cpuid_FMA)
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X86.HasCX16 = isSet(ecx1, cpuid_CX16)
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X86.HasSSE41 = isSet(ecx1, cpuid_SSE41)
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X86.HasSSE42 = isSet(ecx1, cpuid_SSE42)
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X86.HasPOPCNT = isSet(ecx1, cpuid_POPCNT)
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X86.HasAES = isSet(ecx1, cpuid_AES)
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X86.HasOSXSAVE = isSet(ecx1, cpuid_OSXSAVE)
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X86.HasRDRAND = isSet(ecx1, cpuid_RDRAND)
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var osSupportsAVX, osSupportsAVX512 bool
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// For XGETBV, OSXSAVE bit is required and sufficient.
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if X86.HasOSXSAVE {
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eax, _ := xgetbv()
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// Check if XMM and YMM registers have OS support.
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osSupportsAVX = isSet(eax, 1<<1) && isSet(eax, 1<<2)
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if runtime.GOOS == "darwin" {
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// Darwin requires special AVX512 checks, see cpu_darwin_x86.go
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osSupportsAVX512 = osSupportsAVX && darwinSupportsAVX512()
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} else {
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// Check if OPMASK and ZMM registers have OS support.
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osSupportsAVX512 = osSupportsAVX && isSet(eax, 1<<5) && isSet(eax, 1<<6) && isSet(eax, 1<<7)
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}
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}
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X86.HasAVX = isSet(ecx1, cpuid_AVX) && osSupportsAVX
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if maxID < 7 {
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return
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}
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eax7, ebx7, ecx7, edx7 := cpuid(7, 0)
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X86.HasBMI1 = isSet(ebx7, cpuid_BMI1)
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X86.HasAVX2 = isSet(ebx7, cpuid_AVX2) && osSupportsAVX
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X86.HasBMI2 = isSet(ebx7, cpuid_BMI2)
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X86.HasERMS = isSet(ebx7, cpuid_ERMS)
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X86.HasRDSEED = isSet(ebx7, cpuid_RDSEED)
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X86.HasADX = isSet(ebx7, cpuid_ADX)
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X86.HasAVX512 = isSet(ebx7, cpuid_AVX512F) && osSupportsAVX512 // Because avx-512 foundation is the core required extension
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if X86.HasAVX512 {
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X86.HasAVX512F = true
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X86.HasAVX512CD = isSet(ebx7, cpuid_AVX512CD)
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X86.HasAVX512ER = isSet(ebx7, cpuid_AVX512ER)
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X86.HasAVX512PF = isSet(ebx7, cpuid_AVX512PF)
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X86.HasAVX512VL = isSet(ebx7, cpuid_AVX512VL)
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X86.HasAVX512BW = isSet(ebx7, cpuid_AVX512BW)
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X86.HasAVX512DQ = isSet(ebx7, cpuid_AVX512DQ)
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X86.HasAVX512IFMA = isSet(ebx7, cpuid_AVX512IFMA)
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X86.HasAVX512VBMI = isSet(ecx7, cpuid_AVX512_VBMI)
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X86.HasAVX5124VNNIW = isSet(edx7, cpuid_AVX5124VNNIW)
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X86.HasAVX5124FMAPS = isSet(edx7, cpuid_AVX5124FMAPS)
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X86.HasAVX512VPOPCNTDQ = isSet(ecx7, cpuid_AVX512VPOPCNTDQ)
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X86.HasAVX512VPCLMULQDQ = isSet(ecx7, cpuid_AVX512VPCLMULQDQ)
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X86.HasAVX512VNNI = isSet(ecx7, cpuid_AVX512VNNI)
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X86.HasAVX512GFNI = isSet(ecx7, cpuid_AVX512GFNI)
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X86.HasAVX512VAES = isSet(ecx7, cpuid_AVX512VAES)
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X86.HasAVX512VBMI2 = isSet(ecx7, cpuid_AVX512VBMI2)
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X86.HasAVX512BITALG = isSet(ecx7, cpuid_AVX512BITALG)
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}
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X86.HasAMXTile = isSet(edx7, cpuid_AMXTile)
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X86.HasAMXInt8 = isSet(edx7, cpuid_AMXInt8)
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X86.HasAMXBF16 = isSet(edx7, cpuid_AMXBF16)
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// These features depend on the second level of extended features.
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if eax7 >= 1 {
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eax71, _, _, edx71 := cpuid(7, 1)
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if X86.HasAVX512 {
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X86.HasAVX512BF16 = isSet(eax71, cpuid_AVX512BF16)
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}
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if X86.HasAVX {
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X86.HasAVXIFMA = isSet(eax71, cpuid_AVXIFMA)
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X86.HasAVXVNNI = isSet(eax71, cpuid_AVXVNNI)
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X86.HasAVXVNNIInt8 = isSet(edx71, cpuid_AVXVNNIInt8)
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}
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}
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}
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func isSet(hwc uint32, value uint32) bool {
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return hwc&value != 0
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}
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